1. Field of the Invention
The invention relates to a circuit for generating a reference voltage in a semiconductor device and particularly to an internal voltage down converter which produces an internal supply voltage by down-converting an external supply voltage. More particularly, the invention relates to an internal voltage down converter in a dynamic type semiconductor memory device.
2. Description of the Background Art
A semiconductor memory device as a semiconductor device has become highly dense and integrated as its memory capacity increases. These high density and high integration are implemented by way of a micronization technology.
In contrast, the progress of micronization of an LSI (Large Scale Integrated) circuit such as a microprocessor, which determines a system supply voltage, is behind that of semiconductor devices. Thus, as supply voltage of a semiconductor device, 5 V for example is employed, and sufficiently low voltage is not utilized as a supply voltage.
Since components in the semiconductor device are micronized (the design rule is equal to or less than 0.6.about.0.5 .mu.m, for example) by way of micronizing technology, when an externally applied supply voltage is provided to each component as an operating supply voltage, the reliability such as a break-down voltage of an insulating film of MOS transistors as the components cannot be ensured sufficiently. Therefore, in a memory device, such as a DRAM (Dynamic Random Access Memory) having the storage capacity of 16M bits or more, the reliability of elements has been ensured by internally down-converting the external supply voltage.
FIG. 3 is a schematic block diagram illustrating an entire structure of a semiconductor device which is, for example, a dynamic random access memory (DRAM). In FIG. 3, the semiconductor memory device includes an internal voltage down converter 102 generating an internal supply voltage VDD by down-converting an external supply voltage Vcc applied on a power supply line 114 through a supply voltage node 110, an internal circuit 104 operating with the internal supply voltage VDD applied on an internal power supply line 116 from the internal voltage down converter 102 as its operating supply voltage and a circuit 106 using the external supply voltage Vcc on the external power supply line 114 as its operating supply voltage. The internal voltage down converter 102, the internal circuit 104 and the circuit 106 also receive the other supply voltage (hereinafter, simply referred to as a ground voltage) Vss applied on the other power supply line (hereinafter, referred to as a ground line) 118 through a node 112.
The circuit 106 using the external power supply includes a circuit carrying out data input and output. The internal circuit 104 includes a memory cell array. The circuit 106 using the external power supply may include a peripheral circuit. Alternatively, the peripheral circuit may be included in the internal circuit 104.
In general, the internal voltage down converter 102 generates the internal supply voltage VDD by down-converting the external voltage supply Vcc applied on the external power supply line 114. Thus, even though MOS transistor which is a component of the internal circuit 104 is micronized, the reliability of the element can be ensured, as the voltage applied on its gate insulating film is reduced.
FIG. 4 is a diagram showing a specific structure of a conventional internal voltage down converter. In FIG. 4, the internal voltage down converter 102 includes a VREF generation circuit for generating a prescribed reference voltage VREF from the external supply voltage Vcc, a differential amplifier 1 as comparation means for comparing the reference voltage VREF and the internal supply voltage VDD on the internal power supply line 116 and a p-channel MOS transistor 2 feeding a current on the internal power supply line 116 from external supply voltage Vcc in response to an output voltage VG of the differential amplifier 1. The differential amplifier 1 receives the internal supply voltage VDD on the internal power supply line 116 at its positive input, and the reference voltage VREF from the VREF generation circuit 13 at its negative input.
The internal supply voltage VDD from the internal voltage down converter is transferred to the internal circuit 104 in the semiconductor memory device. In FIG. 4, interconnection equivalent circuit 130 of the resistance and the capacitance associated with the internal power supply line 116 is shown together with an equivalent circuit 140 of the internal circuit 104.
The interconnection equivalent circuit 130 includes an interconnection resistance 4 which is connected in series with the internal power supply line 116 and interconnection capacitances 3 and 5 which are connected between the internal power supply line 116 and the ground potential (Vss).
In the internal circuit 104, a MOS transistor carries out a switching operation to charge and discharge an internal node. The charge and discharge are equivalent to charging and discharging a parasitic capacitance. For example, in a DRAM memory cell array, a bit line crossing the selected word line is charged/discharged during a sensing operation. This is equivalent to charging and discharging the capacitance of each bit line. In FIG. 4, such parasitic capacitance is shown as a capacitance 8.
The internal circuit equivalent circuit (load circuit) 140 further includes a load resistance 9 indicative of a constantly existing current path, and a p-channel MOS transistor 6 and n-channel MOS transistor 7 for charging and discharging the capacitance 8 in response to a control signal .phi.. The p-channel MOS transistor 6 charges the capacitance 8 to the internal supply voltage VDD level in response to the control signal .phi.. The n-channel MOS transistor 7 discharges the capacitance to the ground potential level in response to the control signal .phi.. The MOS transistors 6 and 7 operate complementarily. An operation of the internal voltage down circuit 102 will be described.
The p-channel MOS transistor 2 receives the external supply voltage Vcc at its source and supplies a current to the internal power supply line 116 in accordance with the voltage VG applied at the gate from the differential amplifier 1. The differential amplifier 1 generates the output voltage VG by differentially amplifying the reference voltage VREF generated from the VREF generation circuit 13 and the internal supply voltage VDD on the internal power supply line 116.
When the voltage level of the internal supply voltage VDD rises (VDD&gt;VREF), the voltage level of the output voltage VG of the differential amplifier 1 rises and the conductance of p-channel MOS transistor 2 decreases to prevent the internal supply voltage VDD from increasing. In contrast, when the internal supply voltage VDD is decreased and becomes lower than the reference voltage VREF, the output voltage VG of the differential amplifier 1 becomes lower than the prescribed level and increases the conductance of the p-channel MOS transistor 2 and the current is supplied to the internal power supply line 116 to raise the internal supply voltage VDD.
That is, internal voltage down converter 102 feeds back the internal supply voltage VDD to compare the same with the reference voltage VREF and operates to retain the internal supply voltage to a constant voltage level (e.g. the reference voltage VREF level) by amplifying the comparation result to control a power supply driving p-channel MOS transistor 2.
Differential amplifier 1 must have a sufficiently fast response speed, since in the event that the feed back in the feed back loop cannot follow the change of the internal supply voltage VDD, the output voltage VG becomes oscillating state, which may, possibly cause the ripple voltage to be overlaid with the internal supply voltage VDD.
However, since internal power supply line 116 was disposed over whole internal circuit 104, it has been considered that internal supply voltage VDD was smoothed by interconnection resistance 4 and interconnection capacitances 3 and 5, that such ripple voltage could be sufficiently suppressed and that the constant voltage level internal supply voltage VDD could be generated stably also against the transient current. In other words, since the feed back delay of the differential amplifier 1 was sufficiently smaller than an RC time constant of interconnection equivalent circuit 130, it has been considered that the aforementioned ripple voltage could be suppressed reliably (see Nikkei Micro-Device, February, 1990, pp. 115-122).
In internal equivalent circuit (load circuit) 140, when falling the control signal .phi. to "L", the current flows from the internal power supply line 116 to charge capacitance 8. Whenever a capacitive load is driven, phase difference between the load current and the internal supply voltage VDD occurs. (See the relation of I=C.multidot.dV/dt). This load current which flows into the capacitance 8 is supplied via MOS transistor 2 included in internal voltage down converter 102. The current flowing through MOS transistor 2 corresponds to its gate voltage, i.e., output voltage VG of differential amplifier 1. Therefore, the occurrence of the phase difference between the internal supply voltage VDD and the load current is equivalent to the existence of the phase difference between the output voltage VG of differential amplifier 1 and the internal supply voltage VDD. Thus, a delay occurs in the feed back loop included in internal voltage down converter 102, the change of the output voltage VG of differential amplifier 1 is delayed, compared with the change of the internal supply voltage VDD and as shown in FIG. 5, and there occurs a problem that the internal supply voltage VDD vibrates.
FIG. 5 shows the variations of the output voltage of differential amplifier of internal voltage down converter 102 and the internal supply voltage VDD, where ordinate indicates voltage and abscissa indicates time. The circuit simulation is performed assuming the capacitance value of capacitance 8 as 100 pF, the external supply voltage Vcc as 5 V and the reference voltage VREF as 3 V. The resistance value of resistance 9 is about 100.OMEGA..
If the internal supply voltage VDD vibrates, internal circuit 104 cannot operate stably (signal potential variation), which causes the problem of not being able to operate at a high speed (because it is necessary to wait until the signal becomes stable.)
In order to solve the problem of the vibration during a high speed switching operation of the internal supply voltage VDD, Horiguchi et al. have proposed a structure in which a phase compensation circuit 150 having resistance 10 and large capacitance 11 connected in series is provided as a circuit compensating for such a phase difference (IEEE Journal of Solid-State Circuits, Vol. 25, No. 5, October 1990 pp. 1129-1135). In the aforementioned work, Horiguchi et al. have attempted to improve the frequency response characteristics by providing phase compensation circuit 150 to eliminate a pole of differential amplifier 1 and to eliminate the feed back loop (a path of output of transistor 2-internal power supply line-differential amplifier-gate of transistor 2) to increase the phase margin.
However, even though such phase compensation circuit is provided, it cannot completely eliminate the phase difference between the current flowing in transistor 2 and the internal supply voltage VDD during a high speed switching operation, and the change of the output voltage VG of differential amplifier 1 is inevitably delayed behind the change of the internal supply voltage VDD. The satisfactory response characteristics cannot be obtained from the result of the circuit simulation.
In the structure generating reference voltage such as the internal supply voltage with the circuit constituting aforementioned feed back loop, where a load capacitance performs a dynamic operation (an operation including charging and discharging), internal reference voltage cannot be generated stably.
Also, it is difficult to optimize the internal voltage down converter for preventing vibration of the internal reference voltage, since the capacitance value of capacitance (load capacitance 8) associated with internal power supply line 116 differs when internal circuit 104 is in operation than when it is in stand-by.